Renesas Electronics /R7FA6T1AD /AGT0 /AGTMR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as AGTMR1

7 43 0 0 00 0 0 0 0 0 0 0 0 (000)TMOD0 (0)TEDGPL 0 (000)TCK

TCK=000, TEDGPL=0, TMOD=000

Description

AGT Mode Register 1

Fields

TMOD

AGT operating mode select

0 (others): Setting prohibited

0 (000): Timer mode

1 (001): Pulse output mode

2 (010): Event counter mode

3 (011): Pulse width measurement mode

4 (100): Pulse period measurement mode

TEDGPL

AGTIO edge polarity select

0 (0): One edge

1 (1): Both edges

TCK

AGT count source select

0 (others): Setting prohibited

0 (000): PCLKB

1 (001): PCLKB/8

3 (011): PCLKB/2

4 (100): Divided clock LOCO specified by AGTMR2.CKS bit.

5 (101): Underflow event signal from AGT

6 (110): Divided clock fSUB specified by AGTMR2.CKS bit.

Links

()